Crimson Beacon

IP Reuse, Design Management Case Studies: IC Manage

Design Community Ranks IC Manage IP Top in Design Data Management at DAC 2013
 
IC Manage Dean Drako on IP Reuse 2.0 -- Design AND Verification

IC Manage IP Central ranks #2 in Deepchip DAC report 2012  for IP reuse
 
Deepchip DAC report design data management feedback on IC Manage Views Zero-TimeSync, ClioSoft, Methodics
 
AMD, Broadcom, Nvidia, IC Manage on IP Reuse, Design Data Management Best Practices at DAC 2012
 
Broadcom case study: Broadcom discusses using IC Manage for Design Data Management, IP reuse, bug dependency tracing and notification, security, with only 4 hours transition downtime from prior DM system. Plus IC Manage Views™ for EDA tool acceleration, and Zero Time Sync™ workspaces.
 
IC Manage vs. Subversion vs. CVS Shiv Sikand of IC Manage responds to a user, comparing the features of IC Manage GDP with Subversion and open source revision control for digital design.
 
Mid-project transition from Dassault DesignSync to IC Manage
 
Switching from Dassault DesignSync to IC Manage GDP reduced project time by 25%  A semiconductor designer reports on switching from Dassault-Synchronicity DesignSync to IC Manage GDP design data management
 
NVIDIA describes using IC Manage GDP design management to tape out hundreds of chips 
 
SMSC on using IC Manage GDP design data management to manage very large datasets 
 
Biotronik on managing IP reuse with IC Manage GDP (Video) 
 
Comparing ClioSoft SOS to IC Manage GDP A semiconductor designer posts on experiences with both IC Manage GDP and ClioSoft SOS design data management systems
 
National Semiconductor compares IC Manage GDP versus Synchronicity DesignSync, with Cadence Virtuoso
 
GN Resound reports on IC Manage GDP and Cadence Virtuoso, Digital/Analog, Analog/Digital 3rd party IP.

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IP Reuse, Design Management Case Studies: IC Manage